EE4449 Logic Design and Logic Synthesis Lab Courses

EE4449 Logic Design and Logic Synthesis Lab

Labs for EE4449 Logic Design/Logic Synthesis Course at HCMUT

Introduction and Rules

The EE4449 course focuses on logic design and logic synthesis, providing students with hands-on experience in designing, simulating, and synthesizing digital circuits.

• Conduct in group of 2. DO NOT COPY ANYONE. COPY = 0
• File your reports with details: How you did it, why? Test cases, Real Pictures that you took of the kit with a piece of paper containg the dates + Students IDs.
• Reports will be graded and there will be a seperate date for interview grading/demonstration.
• Do not miss more than 1 reports
• Missing deadlines would damage your score.
• Submit your files on LMS. DO NOT EMAIL ME.

Suggestion is you start your lab early before the deadline. The labs are designed so that you cannot complete it in a day (except lab 1). DO NOT WAIT UNTIL DEADLINE TO DO IT. Each Lab would cost ~25 days.

Lab Exercises

The root of this repository contains all the lab exercises for the course. Each lab exercise includes a detailed description, objectives, and step-by-step instructions. All course-related materials are available on LMS

List of Lab Exercises

1. Lab 1: Simple warm-up
2. Lab 2: Matrix problem
3. Lab 3: Asynchronous FIFO
4. Lab 4: Calculator
5. Lab 5: Tensor32 FP